This is a project which is currently making use of HPC facilities at Newcastle University. It is active.
For further information about this project, please contact:
This project focuses on the development and research of compact logic gate network (CLGN) tooling for end-to-end implementation and synthesis. This involves the training, optimisation, synthesis, implementation and place-and-route of CLGNs onto both FPGA and ASIC hardware.
This project utilises Python 3.12 with a mixed open-source and commercial core software stack consisting of: PyTorch using CUDA (v13.0) for GPU accelerated training of the CLGNs, AMD Vivado 2025.2 for synthesis and implementation onto FPGA hardware, and LibreLane (v3.0.3) for our ASIC flow.
Given the substantial amount of GPU compute needed for CLGN training that's not practical on our current dedicated hardware, and CPU compute / memory requirements for synthesis/implementation, we aim to use the HPCs GPU partition for our work.